To store digital data, in recent years, there have been proposed various types of memories utilizing new principles. Particularly, a new type memory utilizing a tunneling magneto resistive (TMR) effect has been well known in the semiconductor field. For example, Roy Scheuerlein et al., have disclosed such TMR elements in a non-patent document titled “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Memory cell” at ISSCC2000 Technical Digest p. 128.
This TMR element is structured by interposing an insulation layer, i.e., a tunnel barrier layer, between a couple of ferromagnetic layers. TMR element can store digit data “1” or “0” by changing a magnetizing direction of the couple of ferromagnetic layers, respectively. Thus, when the couple of ferromagnetic layers are magnetized in the same direction with each other (this is referred as “magnetized in a parallel”), one digit data “1” is stored. On the other hand, when the couple of ferromagnetic layers are magnetized in a reverse direction with each other (this is referred as “magnetized in a counter-parallel”), another digit data “0” is stored.
Generally, a magnetizing direction is fixed for one of the couple of ferromagnetic layers constructing TMR element which is referred to as a fixed layer. Another layer of the couple of ferromagnetic layers is referred to as a free layer since the magnetizing direction is freely able to be changed in a parallel to the fixed layer or in a counter-parallel to the fixed layer in accordance with a change of write data. Thus, the magnetizing direction for the free layer may be changed depending upon a write data for storing digit data “1” or “0” in TMR element.
Also, recently, various device structures and circuit structures of Magneto-resistive Random Access Memory (MRAM) utilizing TMR elements have been proposed. For example, one type of MRAM device structure has been proposed in which a selecting switching element (transistor) is connected to a plurality of TMR elements in order to increase integration density of memory cells and also to improve reading margins as disclosed, for example, in Doll's U.S. Patent Application Publication 2001/0023992A1. The same assigner of this applicant also has proposed a MRAM cell array in which a plurality of TMR elements are connected in a parallel between an upper wiring and a lower wiring as disclosed in Japanese Patent Application Publication 2002-110993 which corresponds to a counter U.S. Patent No 2002/0190291 A1.
FIG. 7 illustrates a plane layout of one example of stacked cell arrays which is constructed by stacking a plurality of cell array planes as suggested in the above-mentioned Japanese Patent Application Publication 2002-110993 filed by the same assignee of the present invention. FIG. 8 is a conceptual cross section view of the stacked cell arrays obtained by cutting along X—X line in FIG. 7.
As illustrated in FIG. 7, each of the plurality of cell array planes includes a plurality of TMR elements 10 being arranged both X and Y directions. The plurality of array planes is stacked on a semiconductor substrate for increasing memory capacity. For simplifying explanations, the stacked cell arrays in this example are constructed by three cell array planes. A top level of the stacked cell array planes is shown by a solid line, a middle cell array plane is shown by a dotted line and a bottom cell array plane is shown by a dashed line. In each of the cell array planes, a plurality of TMR elements 10 is arranged along X-Y directions.
Each of TMR elements 10 is constructed by three layers including an upper free layer, a middle layer and a lower fixed layer. As illustrated in FIG. 8, an upper wiring 11 is connected to each of the free layers of the respective TMR elements 10 in the same plane level, and a lower wiring 12 is connected to each of the fixed layers of the TMR elements 10. Both wirings 11 and 12 extend along the Y (column) direction. In each of the cell array planes, a plurality of TMR elements 10 is disposed in a parallel between the upper wiring 11 and the lower wiring 12 along the X (raw) direction. Each one terminal of the respective lower wirings 12 is connected to one peripheral circuit, such as a sense amplifier (S/A). Each of the another terminals of the respective upper wirings 11 is connected to selection transistors 14, respectively. Namely, a plurality of write wirings 13 is disposed closely upon each of free layers for the respective TMR elements 10 so as to extend along the Y direction in each of the plurality of cell array planes.
In general, a large value of current is required to perform data write and read operations to and from TMR elements due to the characteristics of TMR elements. Particularly, when a plurality of TMR elements is constructed into a miniaturized form, a huge value of write current is required for changing a magnetizing direction of the magnetic layer of the respective TMR elements. It is also required to effectively control a value of a data write current in order to avoid interferences among adjoining cells.
When a plurality of cell array planes are stacked for a miniaturization, each connecting line of the write wirings for the cell arrays arranged on a top plane becomes longer than each connecting line of the write wirings for the memory cell array arranged on a bottom plane in order to connect to a current source for driving write operations. Further, the cell arrays arranged on a top plane require an increased number of contacts. These longer connecting lines and the increased number of contacts cause to increase parasitic wiring resistances. Consequently, the more increased number of TMR element arrays are stacked, the less reduced value of the writing current is generated at the top plane level due to the influences of the increased value of the parasitic wiring resistances. This causes to make difficult to effectively control each value of the writing currents at the respective plane levels. For instance, when a resistance value of a write wiring path of the top plane level becomes three times of a resistance value of a write wiring path of the bottom plane level, the writing current of the top plane level reduces almost one-third of the writing current of the bottom plane level.
This is a serious problem for a stacked cell arrays of TMR elements, since the cell arrays arranged on the top plane level require much more largely increased value of drive current for performing write operations even when the value of the writing current gradually reduces due to a miniaturization of the stacked cell arrays.